IEEE

Implementation of an Optimized AXI using Verilog

Abstract: Optimization of Throughput and Delay is a crucial need in any SoC system. In order to achieve an appreciable performance in the exchange of data between the components of a AXI(advanced ...
IEEE

Design and Implementation of 32-bit RISC-V Processor Using Verilog

Abstract: The design and implementation of a 32-bit single-cycle RISC-V processor in Verilog is a sophisticated and elaborate process that aims to create a functioning processor architecture that ...